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? 2002 microchip technology inc. ds21166f-page 1 m 24aa52/24lcs52 features ? single supply with operation down to 1.8v ? low power cmos technology - 1 ma active current typical - 1 a standby current typical (i-temp) ? organized as 1 block of 256 bytes (256 x 8) ? software write protection for lower 128 bytes ? hardware write protection for entire array ? 2-wire serial interface bus, i 2 c? compatible ? schmitt trigger inputs for noise suppression ? output slope control to eliminate ground bounce ? 100 khz (24aa52) and 400 khz (24lcs52) compatibility ? self-timed write cycle (including auto-erase) ? page-write buffer for up to 16 bytes ? 3.5 ms typical write cycle time for page-write ? esd protection > 4,000v ? 1,000,000 erase/write cycles ? data retention > 200 years ? 8-lead pdip, soic, tssop and msop package ? available for extended temperature ranges: - industrial (i): -40c to +85c device selection table package types description the microchip technology inc. 24aa52/24lcs52 (24xx52*) is a 2 kbit electrically erasable prom capable of operation across a broad voltage range (1.8v to 5.5v). this device has a software write protect feature for the lower half of the array, as well as an external pin that can be used to write protect the entire array. the software write protect feature is enabled by sending the device a special command. once this fea- ture has been enabled, it cannot be reversed. in addi- tion to the software protect feature, there is a wp pin that can be used to write protect the entire array, regardless of whether the software write protect regis- ter has been written or not. this allows the system designer to protect none, half or all of the array, depending on the application. the device is organized as one block of 256 x 8-bit memory with a 2-wire serial interface. low voltage design permits operation down to 1.8v, with standby and active currents of only 1 a and 1 ma respectively. the 24xx52 also has a page- write capability for up to 16 bytes of data. the 24xx52 is available in the standard 8-pin pdip, surface mount soic, tssop and msop packages. block diagram part number v cc range max clock frequency temp ranges 24aa52 1.8-5.5 400 khz (1) i 24lcs52 2.5-5.5 400 khz i note 1: 100 khz for v cc <2.5v 24xx52 a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc wp scl sda pdip/soic/tssop/msop i/o control logic memory control logic xdec hv generator standard array software write write protect circuitry ydec v cc v ss sense amp r/w control sda scl a0 a1 a2 wp protected area (00h-7fh) 2k i 2 c ? serial eeprom with software write protect *24xx52 is used in this document as a generic part number for the 24aa52/24lcs52 devices.
24aa52/24lcs52 ds21166f-page 2 ? 2002 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings? v cc ............................................................................................................................... ..............................................6.5v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.3v to v cc +1.0v storage temperature ............................................................................................................ ...................-65c to +150c ambient temp. with power applied ............................................................................................... ...........-40c to +125c esd protection on all pins ............................................................................................................................... ....................... 4kv ? notice: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 1-1: dc specifications dc characteristics v cc = +1.8v to +5.5v industrial (i): t amb = -40c to +85c param. no. symbol characteristic min typ max units conditions d1 v ih a0, a1, a2, scl, sda and wp pins ????? d2 ? high level input voltage 0.7 v cc ??v? d3 v il low level input voltage ? ? 0.3 v cc v0.2 v cc for v cc < 2.5v d4 v hys hysteresis of schmitt trigger inputs 0.05 v cc ??v( note ) d5 v ol low level output voltage ? ? 0.40 v i ol = 3.0 ma, v cc = 2.5v d6 i li input leakage current ? ? 10 ma v in = 0.1v to v cc d7 i lo output leakage current ? ? 10 a v out = 0.1v to v cc d8 c in , c out pin capacitance (all inputs/outputs) ? ? 10 pf v cc = 5.0v ( note ) t amb = 25c, f clk = 1 mhz d9 i cc write operating current ? 1.0 3.0 ma v cc = 5.5v, scl = 400 khz d10 i cc read ? 0.20 1.0 ma ? d11 i ccs standby current ? ? 0.36 ? 1.0 ? a industrial sda = scl = v cc a0, a1, a2, wp = v ss note: this parameter is periodically sampled and not 100% tested.
? 2002 microchip technology inc. ds21166f-page 3 24aa52/24lcs52 table 1-2: ac specifications ac characteristics v cc = +1.8v to +5.5v industrial (i): t amb = -40c to +85c param. no. symbol characteristic min typ max units conditions 1f clk clock frequency ? ? ? ? 400 100 khz 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa52) 2t high clock high time 600 4000 ? ? ? ? ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa52) 3t low clock low time 1300 4700 ? ? ? ? ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa52) 4t r sda and scl rise time (note 1) ? ? ? ? 300 1000 ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa52) 5t f sda and scl fall time ? ? ? 300 ns ( note 1 ) 6t hd : sta start condition hold time 600 4000 ? ? ? ? ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa52) 7t su : sta start condition setup time 600 4700 ? ? ? ? ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa52) 8t hd : dat data input hold time 0 ? ? ?ns( note 2 ) 9t su : dat data input setup time 100 250 ? ? ? ? ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa52) 10 t su : sto stop condition setup time 600 4000 ? ? ? ? ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa52) 11 t aa output valid from clock (note 2) ? ? ? ? 900 3500 ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa52) 12 t buf bus free time: time the bus must be free before a new transmission can start 1300 4700 ? ? ? ? ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa52) 13 t of output fall time from v ih minimum to v il maximum 20+0.1c b ? ? ? 250 250 ns 2.5v v cc 5.5v 1.8v v cc < 2.5v (24aa52) 14 t sp input filter spike suppression (sda and scl pins) ??50ns( note 1 and note 3 ) 15 t wc write cycle time (byte or page) ??5ms? 16 ? endurance 1m ? ? cycles 25c, v cc = 5.0v, block mode (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs, which provide improved noise spike suppression. this eliminates the need for a t i specification for standard operation. 4: this parameter is not tested but ensured by characterization. for endurance estimates in a specific appli- cation, please consult the total endurance model which can be obtained on microchip?s website: www.microchip.com.
24aa52/24lcs52 ds21166f-page 4 ? 2002 microchip technology inc. figure 1-1: bus timing data figure 1-2: bus timing start/stop 7 5 2 4 8 910 12 11 14 6 scl sda in sda out 3 7 6 d4 10 start stop scl sda
? 2002 microchip technology inc. ds21166f-page 5 24aa52/24lcs52 2.0 functional description the 24xx52 supports a bi-directional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. the bus has to be con- trolled by a master device, which generates the serial clock (scl), controls the bus access and generates the start and stop conditions, while the 24xx52 works as slave. both master and slave can operate as trans- mitter or receiver, but the master device determines which mode is activated. 3.0 bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 3-1). 3.1 bus not busy (a) both data and clock lines remain high. 3.2 start data transfer (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 3.3 stop data transfer (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 3.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is determined by the master device and is, theoretically, unlimited; although only the last sixteen will be stored when doing a write operation. when an overwrite does occur, it will replace data in a first-in, first-out (fifo) fashion. 3.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse, which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (24xx52) will leave the data line high to enable the master to generate the stop con- dition. figure 3-1: data transfer sequence on the serial bus note: the 24xx52 does not generate any acknowledge bits if an internal programming cycle is in progress. scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition
24aa52/24lcs52 ds21166f-page 6 ? 2002 microchip technology inc. 3.6 device addressing a control byte is the first byte received following the start condition from the master device. the first part of the control byte consists of a 4-bit control code which is set to 1010 for normal read and write operations and 0110 for writing to the write protect register. the control byte is followed by three chip select bits (a2, a1, a0). the chip select bits allow the use of up to eight 24xx52 devices on the same bus and are used to determine which device is accessed. the chip select bits in the control byte must correspond to the logic levels on the corresponding a2, a1 and a0 pins for the device to respond. the device will not acknowledge if you attempt a read command with the control code set to 0110 . the eighth bit of slave address determines if the master device wants to read or write to the 24xx52 (figure 3-2). when set to a one, a read operation is selected. when set to a zero, a write operation is selected. figure 3-2: control byte allocation 4.0 write operations 4.1 byte write following the start signal from the master, the device code(4 bits), the chip select bits (3 bits) and the r/w bit, which is a logic low, are placed onto the bus by the mas- ter transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow once it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24xx52. after receiving another acknowledge signal from the 24xx52, the master device will transmit the data word to be written into the addressed memory location. the 24xx52 acknowl- edges again and the master generates a stop condition. this initiates the internal write cycle, which means that, during this time, the 24xx52 will not generate acknowl- edge signals (figure 4-1). if an attempt is made to write to the array when the software or hardware write protec- tion has been enabled, the device will acknowledge the command but no data will be written. the write cycle time must be observed even if the write protection is enabled. 4.2 page write the write control byte, word address and the first data byte are transmitted to the 24xx52 in the same way as in a byte write. instead of generating a stop condition, the master transmits up to 15 additional data bytes to the 24xx52, which are temporarily stored in the on- chip page buffer and will be written into the memory after the master has transmitted a stop condition. upon receipt of each word, the four lower order address pointer bits are internally incremented by one. the higher order four bits of the word address remain con- stant. if the master should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received, an internal write cycle will begin (figure 4-2). if an attempt is made to write to the array when the hardware write protection has been enabled, the device will acknowledge the command but no data will be written. the write cycle time must be observed even if the write protection is enabled. operation control code chip select r/w read 1010 a2 a1 a0 1 write 1010 a2 a1 a0 0 set write protect register 0110 a2 a1 a0 0 or start read/write slave address r/w a 101 0 a2 a1 a0 011 0 a2 a1 a0 note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multi- ples of the page buffer size (or ?page size?) and end at addresses that are integer mul- tiples of [page size - 1]. if a page write com- mand attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the cur- rent page (overwriting data previously stored there), instead of being written to the next page, as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
? 2002 microchip technology inc. ds21166f-page 7 24aa52/24lcs52 figure 4-1: byte write figure 4-2: page write s p bus activity master sda line bus activity s t a r t s t o p control byte word address data a c k a c k a c k s p bus activity master sda line bus activity s t a r t control byte word address (n) data (n) data (n + 15) s t o p a c k a c k a c k a c k a c k data (n + 1)
24aa52/24lcs52 ds21166f-page 8 ? 2002 microchip technology inc. 5.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master send- ing a start condition followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 5-1 for flow diagram. figure 5-1: acknowledge polling flow 6.0 write protection the 24xx52 has a software write protect feature that allows the lower half of the array (addresses 00h - 7fh ) to be permanently write protected, as well as a wp pin that can be used to protect the entire array. 6.1 software write protect the software write protect feature is invoked by writing to the write protect register. this is done by sending a command similar to a normal write command. as shown in figure 6-1, the write protect register is written by sending a write command with the slave address set to 0110 instead of 1010 and the address bits and data bits are don?t cares. once the software write protect register has been written, the device will not acknowledge the 0110 control byte. 6.2 hardware write protect the wp pin can be tied to v cc , v ss or can be left float- ing. if tied to v cc , the entire array will be write pro- tected, regardless of whether the software write protect register has been written or not. if the wp pin is set to v cc , it will prevent the software write protect register from being written. if the wp is tied to v ss or left float- ing, then write protection is determined by the status of the software write protect register. figure 6-1: setting write protect register send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes note: once the software write protect register has been written, the write protection is enabled and cannot be reversed, even if the device is powered down. s p bus activity master sda line bus activity s t a r t s t o p control byte word address data a c k a c k a c k
? 2002 microchip technology inc. ds21166f-page 9 24aa52/24lcs52 7.0 read operation read operations are initiated in the same way as write operations, with the exception that the r/w bit of the slave address is set to ? 1 ?. there are three basic types of read operations: current address read, random read and sequential read. 7.1 current address read the 24xx52 contains an address counter that main- tains the address of the last word accessed, internally incremented by ? 1 ?. therefore, if the previous access (either a read or write operation) was to address n , the next current address read operation would access data from address n+1 . upon receipt of the slave address with r/w bit set to ? 1 ?, the 24xx52 issues an acknowl- edge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24xx52 discontinues transmission (figure 7-1). 7.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, the word address must first be set. this is done by sending the word address to the 24xx52 as part of a write operation. once the word address is sent, the master generates a start condi- tion following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. the master then issues the control byte again, but with the r/w bit set to a ? 1 ?. the 24xx52 then issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the trans- fer but does generate a stop condition and the 24xx52 discontinues transmission (figure 7-2). 7.3 sequential read sequential reads are initiated in the same way as a ran- dom read, with the exception that after the 24xx52 transmits the first data byte, the master issues an acknowledge, as opposed to a stop condition in a random read. this directs the 24xx52 to transmit the next sequentially addressed 8-bit word (figure 7-3). to provide sequential reads, the 24xx52 contains an internal address pointer, which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 7.4 contiguous addressing across multiple devices the chip select bits (a2, a1, a0) can be used to expand the contiguous address space for up to 16k bits by adding up to eight 24xx52 devices on the same bus. in this case, software can use a0 of the control byte as address bit a8, a1 as address bit a9 and a2 as address bit a10. it is not possible to sequentially read across device boundaries. 7.5 noise protection and brown out the 24xx52 employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below 1.5v at nominal conditions. the scl and sda inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. figure 7-1: current address read sp bus activity master sda line bus activity s t o p control byte data (n) a c k n o a c k s t a r t
24aa52/24lcs52 ds21166f-page 10 ? 2002 microchip technology inc. figure 7-2: random read figure 7-3: sequential read s p s bus activity master sda line bus activity s t a r t s t o p control byte a c k word address (n) control byte s t a r t data (n) a c k a c k n o a c k p bus activity master sda line bus activity s t o p control byte a c k n o a c k data (n) data (n + 1) data (n + 2) data (n + x) a c k a c k a c k
? 2002 microchip technology inc. ds21166f-page 11 24aa52/24lcs52 8.0 pin descriptions the descriptions of the pins are listed in table 8-1. table 8-1: pin function table 8.1 a0, a1, a2 the levels on these inputs are compared with the cor- responding bits in the slave address. the chip is selected if the compare is true. up to eight 24xx52 devices may be connected to the same bus by using different chip select bit combina- tions. these inputs must be connected to either v ss or v cc . 8.2 serial address/data input/output (sda) this is a bi-directional pin used to transfer addresses and data into and data out of the device. it is an open drain terminal. therefore, the sda bus requires a pull- up resistor to v cc (typical 10 k ? for 100 khz, 2 k ? for 400 khz). for normal data transfer, sda, is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 8.3 serial clock (scl) this input is used to synchronize the data transfer to and from the device. 8.4 write-protect (wp) this is the hardware write protect pin. it can be tied to v cc , v ss or be left floating. if tied to v cc , the hardware write protection is enabled. if the wp pin is tied to v ss , the hardware write protection is disabled. if the wp pin is left floating, an internal pull down logic will pull the wp pin to v ss and the hardware write protection will be disabled. symbol pdip soic tssop msop description a0 1 1 1 1 chip address input a1 2 2 2 2 chip address input a2 3 3 3 3 chip address input v ss 4 4 4 4 ground sda 5 5 5 5 serial address/data i/o scl 6 6 6 6 serial clock wp 7 7 7 7 write protect input v cc 8 8 8 8 +1.8v to 5.5v power supply
24aa52/24lcs52 ds21166f-page 12 ? 2002 microchip technology inc. 9.0 packaging information 9.1 package marking information xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example: 8-lead soic (150 mil) example: xxxxxxxx xxxxyyww nnn 24aa52 i/pnnn yyww 24lcs52 i/snyyww nnn 8-lead msop example: xxxxxx ywwnnn 4s52i ywwnnn legend: xx...x customer specific information * yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard otp marking consists of microchip part number, year code, week code and traceability code. 8-lead tssop example: xxxx xyww nnn s52 iyww nnn
? 2002 microchip technology inc. ds21166f-page 13 24aa52/24lcs52 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
24aa52/24lcs52 ds21166f-page 14 ? 2002 microchip technology inc. 8-lead plastic small outline (sn) ? narrow, 150 mil (soic) foot angle f 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 f a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
? 2002 microchip technology inc. ds21166f-page 15 24aa52/24lcs52 8-lead plastic thin shrink small outline (st) ? 4.4 mm (tssop) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 3.10 3.00 2.90 .122 .118 .114 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters* inches units a2 a a1 l c f 1 2 d n p b e e1 foot angle f 048048 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-086 significant characteristic
24aa52/24lcs52 ds21166f-page 16 ? 2002 microchip technology inc. 8-lead plastic micro small outline package (msop) d l c dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not .037 .035 f footprint (reference) exceed.010? (0.254mm) per side. notes: drawing no. c04-111 *controlling parameter mold draft angle top mold draft angle bottom foot angle lead width lead thickness c b 7 7 .004 .010 0 .006 .012 (f) dimension limits overall height molded package thickness molded package width overall length foot length standoff overall width number of pins pitch a l e1 d a1 e a2 .016 .114 .114 .022 .118 .118 .002 .030 .193 .034 min p n units .026 nom 8 inches 1.00 0.95 0.90 .039 0.15 0.30 .008 .016 6 0.10 0.25 0 7 7 0.20 0.40 6 millimeters* 0.65 0.86 3.00 3.00 0.55 4.90 .044 .122 .028 .122 .038 .006 0.40 2.90 2.90 0.05 0.76 min max nom 1.18 0.70 3.10 3.10 0.15 0.97 max 8 e1 e b n 1 2 significant characteristic .184 .200 4.67 .5.08
? 2002 microchip technology inc. ds21166f-page 17 24aa52/24lcs52 systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. on-line support microchip provides on-line support on the microchip world wide web (www) site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favorite internet browser to attach to: www.microchip.com the file transfer site is available by using an ftp ser- vice to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: ? latest microchip press releases ? technical support section with frequently asked questions ? design tips ? device errata ? job postings ? microchip consultant program member listing ? links to other useful web sites related to microchip products ? conferences for products, development systems, technical information and more ? listing of seminars and events 013001
24aa52/24lcs52 ds21166f-page 18 ? 2002 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21166f 24aa52/24lcs52
? 2002 microchip technology inc. ds21166f-page19 24aa52/24lcs52 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. sales and support data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. part no. x /xx package temperature range device device: 24aa52: = 1.8v, 2 kbit i 2 c serial eeprom 24aa52t: = 1.8v, 2 kbit i 2 c serial eeprom (tape and reel) 24lcs52: = 2.5v, 2 kbit i 2 c serial eeprom 24lcs52t: = 2.5v, 2 kbit i 2 c serial eeprom (tape and reel) temperature range: i=-40c to +85c package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead st = plastic tssop (4.4 mm), 8-lead ms = plastic micro small outline (msop), 8-lead examples: a) 24aa52-i/p: industrial temperature, pdip package b) 24aa52-i/sn: industrial temperature, soic package c) 24aa52t-i/ms: tape and reel, industrial temperature, msop package a) 24lcs52-i/p: industrial temperature, pdip package b) 24lcs52-i/sn: industrial temperature, soic package c) 24lcs52t-i/ms: tape and reel, indus- trial temperature, msop package
24aa52/24lcs52 ds21166f-page 20 ? 2002 microchip technology inc. notes:
? 2002 microchip technology inc. ds21166f-page 21 24aa52/24lcs52 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchip?s products as critical com- ponents in life support systems is not authorized except with express written approval by microchip. no licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, filterlab, k ee l oq , microid, mplab, pic, picmicro, picmaster, picstart, pro mate, seeval and the embedded control solutions company are registered trademarks of microchip tech- nology incorporated in the u.s.a. and other countries. dspic, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, microport, migratable memory, mpasm, mplib, mplink, mpsim, mxdev, picc, picdem, picdem.net, rfpic, select mode and total endurance are trademarks of microchip technology incorporated in the u.s.a. serialized quick turn programming (sqtp) is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2002, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999 and mountain view, california in march 2002. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, non-volatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001 certified.
ds21166f-page 22 ? 2002 microchip technology inc. m americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: 480-792-7627 web address: http://www.microchip.com rocky mountain 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7966 fax: 480-792-7456 atlanta 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston 2 lan drive, suite 120 westford, ma 01886 tel: 978-692-3848 fax: 978-692-3821 chicago 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas 4570 westgrove drive, suite 160 addison, tx 75001 tel: 972-818-7423 fax: 972-818-2924 detroit tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 kokomo 2767 s. albright road kokomo, indiana 46902 tel: 765-864-8360 fax: 765-864-8387 los angeles 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 toronto 6285 northam drive, suite 108 mississauga, ontario l4v 1x5, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia microchip technology australia pty ltd suite 22, 41 rawson street epping 2121, nsw australia tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing microchip technology consulting (shanghai) co., ltd., beijing liaison office unit 915 bei hai wan tai bldg. no. 6 chaoyangmen beidajie beijing, 100027, no. china tel: 86-10-85282100 fax: 86-10-85282104 china - chengdu microchip technology consulting (shanghai) co., ltd., chengdu liaison office rm. 2401, 24th floor, ming xing financial tower no. 88 tidu street chengdu 610016, china tel: 86-28-86766200 fax: 86-28-86766599 china - fuzhou microchip technology consulting (shanghai) co., ltd., fuzhou liaison office unit 28f, world trade plaza no. 71 wusi road fuzhou 350001, china tel: 86-591-7503506 fax: 86-591-7503521 china - shanghai microchip technology consulting (shanghai) co., ltd. room 701, bldg. b far east international plaza no. 317 xian xia road shanghai, 200051 tel: 86-21-6275-5700 fax: 86-21-6275-5060 china - shenzhen microchip technology consulting (shanghai) co., ltd., shenzhen liaison office rm. 1315, 13/f, shenzhen kerry centre, renminnan lu shenzhen 518001, china tel: 86-755-2350361 fax: 86-755-2366086 china - hong kong sar microchip technology hongkong ltd. unit 901-6, tower 2, metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2401-1200 fax: 852-2401-3431 india microchip technology inc. india liaison office divyasree chambers 1 floor, wing a (a3/a4) no. 11, o?shaugnessey road bangalore, 560 025, india tel: 91-80-2290061 fax: 91-80-2290062 japan microchip technology japan k.k. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa, 222-0033, japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea 135-882 tel: 82-2-554-7200 fax: 82-2-558-5934 singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore, 188980 tel: 65-6334-8870 fax: 65-6334-8850 ta iw a n microchip technology taiwan 11f-3, no. 207 tung hua north road taipei, 105, taiwan tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe denmark microchip technology nordic aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany microchip technology gmbh gustav-heinemann ring 125 d-81739 munich, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 united kingdom microchip ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5869 fax: 44-118 921-5820 05/01/02 *ds21166f* w orldwide s ales and s ervice

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